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| www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 1 1.1 * * * * * * * * * * * * Introduction Features * * 16-, 20-, 24-, and 32-Bit Word Sizes 64-fS, 128-fS, 192-fS, and 256-fS SCLK to Support Discrete, 4-Channel TDM, 6-Channel TDM, and 8-Channel TDM Data-Transfer Formats Two I2C Ports for Slave or Master Download Soft Volume Controller Dither Generator Efficient log2/2x Estimator Single 3.3-V Power Supply 38-Pin TSSOP Package (DCP) AEC-Q100 (Grade 2: -40C to 105C) Compliant for Automotive Applications (TAS3108IA) 8-Channel Programmable Audio Digital Signal Processor (DSP) 135-MHz Maximum Speed, >2800 Processing Cycles per Sample at 48 kHz Sample Rates of 32 kHz to 192 kHz 48-Bit Data Path and 28-Bit Coefficients Single-Cycle, 76-Bit Multiply Accumulate Five Simultaneous Operations per Clock Cycle 1022 Words of 48-Bit Data Memory 1022 Words of 28-Bit Coefficient Memory 3K Words of 54-Bit Program RAM 5.88K Words of 24-Bit Delay Memory (122.5 ms at 48 kHz) 15 Stereo/TDM Data Formats Independent Input/Output Data Formats * * * * * * * 1.2 * * * * Applications Automotive Sound Systems Digital Televisions Home Theater Systems Mini-Component Audio TAS3108/TAS3108IA SDIN1 SDIN2 SDIN3 SDIN4 Serial Audio Input Port Audio DSP Core 8 48-Bit Data Path 28-Bit Coefficients 76-Bit MAC 3K Code RAM 1K Data RAM 1K Coeff. RAM 5.8K Delay RAM Boot ROM Volume Update 8051 MCU I2C Port #1 I2C Port #2 I2C Interface 8-Bit Microprocessor 256 IRAM 2K ERAM 12K Code RAM B0074-01 8 Serial Audio Output Port SDOUT1 SDOUT2 SDOUT3 SDOUT4 MCLK LRCLK SCLKIN SCLKOUT1 SCLKOUT2 PLL and Clock Control Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2006, Texas Instruments Incorporated TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com Contents 1 Introduction ............................................... 1 1.1 1.2 Features .............................................. 1 Applications........................................... 1 7 I2C Register Map........................................ 34 7.1 7.2 7.3 7.4 Clock Control Register (0x00) ...................... 35 2 Functional Description 2.1 2.2 2.3 2.4 2.5 2.6 2.7 ................................. 3 Device Description.................................... 3 Power Supply ......................................... 4 Clock Control ......................................... 4 Serial Audio Ports (SAPs) ............................ 4 M8051Warp Microprocessor.......................... 4 I2C Control Interface.................................. 4 Audio DSP Core ...................................... 5 Status Register (0x02) .............................. 38 I2C Memory Load Control and Data Registers (0x04 and 0x05)............................................ 39 Memory Access Registers (0x06 and 0x07) ........ 40 8 Electrical Specifications .............................. 41 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 Absolute Maximum Ratings Over Operating Temperature Range (unless otherwise noted) ...... 41 Package Dissipation Ratings (TAS3108/TAS3108IA) .............................. 41 Recommended Operating Conditions (TAS3108/TAS3108IA) .............................. 41 Electrical Characteristics (TAS3108/TAS3108IA) ... 42 Timing Characteristics............................... 43 43 44 45 46 3 Physical Characteristics 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 ............................... Terminal Assignments ................................ Terminal Descriptions ................................ Reset (RESET) ....................................... 5 5 6 6 Power-On Reset (RESET)............................ 7 Power Down (PDN)................................... 7 I2C Bus Control (CS0) ................................ 7 Programmable I/O (GPIO)............................ 7 Input and Output Serial Audio Ports.................. 8 Master Clock Signals (TAS3108/TAS3108IA) ..... Serial Audio Port Slave Mode Signals (TAS3108/TAS3108IA) .............................. 8.5.3 Serial Audio Port Master Mode Signals (TAS3108/TAS3108IA) .............................. 8.5.4 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices.......... 8.5.6 4 5 6 Algorithm and Software Development Tools for TAS3108/TAS3108IA ................................... 17 Clock Controls .......................................... 17 Microprocessor Controller .......................... 24 6.1 6.2 6.3 Reset Timing (TAS3108/TAS3108IA) .............. 48 Schematics .......................................... 49 Recommended Oscillator Circuit .................... 51 Recommended PCB Design for TAS3108IA Applications ......................................... 51 9 Application Information ............................... 49 9.1 9.2 9.3 ............................. 2C Operation .............................. Detailed I I2C Master-Mode Device Initialization .............. General I2C Operations 25 26 28 2 Contents www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 2 2.1 Functional Description Device Description The TAS3108/TAS3108IA is a fully programmable high-performance audio processor. It uses an efficient, custom, multi-instruction programming environment optimized for digital audio processing algorithms. The TAS3108/TAS3108IA architecture provides high-quality audio processing by using a 48-bit data path, 28-bit filter coefficients, and a single-cycle 28 x 48-bit multiplier with a 76-bit accumulator. An embedded 8051 microprocessor provides algorithm and data control for the TAS3108/TAS3108IA. The TAS3108 is the commercial version intended for home audio and other commercial applications. The TAS3108IA is the automotive version that is qualified for use in automotive applications. Audio DSP Core 8 Channels 28 SDIN1 SDIN2 SDIN3 SDIN4 Serial Audio Port SDOUT1 SDOUT2 SDOUT3 SDOUT4 Coef. RAM (1022 y 28) Data Path 48 Data RAM (1022 y 48) 8 Channels 48 MCLK LRCLK SCLKIN SCLKOUT1 SCLKOUT2 Clock Control Controller 54 Memory Interface Code RAM (3K y 54) Microprocessor Core Internal Data RAM (256 y 8) 8 Delay Memory (5.8K y 24) External Data RAM (2048 y 8) 8-Bit MCU (8051) Control Registers 8 Volume Update 2ySDA I2C Control Interface 2ySCL CSO GPIO AVDD DVDD 8 Code RAM (12K y 8) Code ROM Power Supply B0075-01 Figure 2-1. Expanded TAS3108/TAS3108IA Functional Block Diagram Functional Description 3 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 2.2 Power Supply The power supply contains supply regulators that provide analog and digital regulated power for various sections of the TAS3108/TAS3108IA. Only one external 3.3-V supply is required. All other voltages are generated on-chip from the external 3.3-V supply. 2.3 Clock Control The TAS3108/TAS3108IA can be an audio data clock-master or clock-slave device. In clock-master mode it generates MCLK, SCLK, and LRCLK. In clock-slave mode it accepts MCLK, SCLK, and LRCLK. It can generate or accept master clocks from 6 MHz to 24.576 MHz. Master or slave operation is set via I2C register 0x00. The TAS3108/TAS3108IA can use a 6- to 20-MHz crystal or a 6- to 24.576-MHz, 3.3-V MCLKI digital input as the master clock in either clock-master or clock-slave mode. In clock-slave mode, the master clock frequency does not need to be an integer multiple of the sample rate. The TAS3108/TAS3108IA does not support clock error detection. If a clock error occurs, the TAS3108/TAS3108IA does not prevent invalid data or clocks from being output. This means that the application system must be designed to handle clock errors. 2.4 Serial Audio Ports (SAPs) Serial audio data is input via pins SDIN1, SDIN2, SDIN3, and SDIN4. Serial audio data is output on pins SDOUT1, SDOUT2, SDOUT3, and SDOUT4. The TAS3108/TAS3108IA accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, or 192-kHz serial data as 16-, 20-, 24-, or 32-bit data in left-justified, right-justified, or I2S serial data formats. All four ports accommodate these three 2-channel data formats. In addition to supporting the 2-channel formats, SDIN1 and SDOUT1 also provide support for time-division multiplex (TDM) data formats of 4, 6, or 8 channels. The data formats are selectable via I2C register 0x00. All input channels must use the same data format. All output channels must use the same data format. However, the input and output formats can be different. 2.5 M8051Warp Microprocessor The M8051Warp (8051) microprocessor controls I2C reads and writes and participates in some audio processing tasks requiring multiframe (fS period) processing cycles. The 8051 processor performs some control calculations and exchanges data between the audio DSP core and the I2C interface. It also provides mode control for the SAP interface and clock control. The microcode can program the GPIO pin for post-boot-up operation to be an input or an output. For more information, see the TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067). 2.6 I2C Control Interface The TAS3108/TAS3108IA has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and providing status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to download programs and data from external memory such as an EEPROM. See Section 6 for more information. 4 Functional Description www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 2.7 Audio DSP Core The audio DSP core arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks. The primary features of the audio DSP core are: * 48-bit data path with 76-bit accumulator * Hardware multiplier (28-bit x 48-bit) * Read/write, single-cycle memory access * Input is 48-bit, 2s-complement data, multiplexed in from the SAP immediately following an LRCLK pulse. * Output is 32-bit, 2s-complement data on four buses. * Separate control for writing to delay memory * Separate coefficient memory (28-bit) and data memory (48-bit) * Linear feedback shift register (LFSR) is a random-number generator which can be used to dither the audio. * Coefficient RAM, data RAM, LFSR seed, program counter, and memory pointers are all mapped into the same 5.88K memory space for convenient addressing by the microprocessor. * Memory interface block contains four pointers, two for data memory and two for coefficient memory. The audio DSP core is used to implement all audio processing functions. 3 3.1 Physical Characteristics Terminal Assignments DCP PACKAGE (TOP VIEW) AVSS VR_PLL XTALI XTALO MCLKI MICROCLK_DIV CS0 GPIO DVDD DVSS SDIN1 SDIN2 SDIN3 SDIN4 SDA1 SCL1 SDA2 SCL2 LRCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 AVDD RESERVED PLL2 PLL1 PLL0 RESERVED RESET PDN DVDD DVSS VR_DIG SDOUT1 SDOUT2 SDOUT3 SDOUT4 SCLKOUT2 SCLKOUT1 MCLKO SCLKIN P0033-01 Physical Characteristics 5 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 3.2 Terminal Descriptions TERMINAL NAME AVDD AVSS CS0 DVDD DVSS GPIO LRCLK MCLKIN MCLKO NO. 38 1 7 9, 30 10, 29 8 19 5 21 6 31 34 35 36 33, 37 32 16 18 20 22 23 15 17 11 12 13 14 27 26 25 24 2 3 4 28 O O I I/O I/O I O O I/O I/O I I I I O O O O Pulldown Pulldown Pulldown Pulldown Pulldown Pullup I/O I/O I O I I I I I Pulldown Pullup Pullup Pulldown Pullup Pullup Pulldown I Pulldown INPUT/ OUTPUT (1) PULLUP/ PULLDOWN (2) DESCRIPTION Analog power-supply input (3.3-V) Analog ground Chip select Digital power-supply input (3.3-V) Digital ground GPIO control pin (user programmable) Sample rate clock (fS) input or output Master clock input (Connect to ground when not in use.) Master clock output Internal microprocessor clock divide control Powers down all logic and stops all clocks, active-low. Coefficient memory remains stable through power-down cycle. PLL control 0 PLL control 1 PLL control 2 Connect to ground Reset, active-low I2C port #1 clock (always a slave) I2C port #2 clock (always a master) Bit clock input Bit clock #1 out. Used to receive input serial data. Bit clock #2 out. Used to clock output serial data. I2C port #1 data (always a slave) I2C port #2 data (always a master) Serial data input 1 Serial data input 2 Serial data input 3 Serial data input 4 Serial data output 1 Serial data output 2 Serial data output 3 Serial data output 4 Internal regulator. This pin must not be used to power external devices. Oscillator input (connect to ground when not in use) Oscillator output Internal regulator. This pin must not be used to power external devices. MICROCLK_DIV PDN PLL0 PLL1 PLL2 RESERVED RESET SCL1 SCL2 SCLKIN SCLKOUT1 SCLKOUT2 SDA1 SDA2 SDIN1 SDIN2 SDIN3 SDIN4 SDOUT1 SDOUT2 SDOUT3 SDOUT4 VR_PLL XTALI XTALO VR_DIG (1) (2) I = input; O = output All pullups are 20-A weak pullups, and all pulldowns are 20-A weak pulldowns. The pullups and pulldowns are included to ensure proper input logic levels if the terminals are left unconnected (pullups logic 1 input; pulldowns logic 0 input). Devices that drive inputs with pullups must be able to sink 20 A while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be able to source 20 A while maintaining a logic-1 drive level. 3.3 Reset (RESET) The RESET pin is an asynchronous control signal that restores all TAS3108/TAS3108IA components to the default configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051 starts initialization. A valid MCLKI or XTLI must be present when clearing the RESET pin to initiate a device reset. A reset can be initiated by applying a logic 0 on the reset pin, RESET. A reset can also be issued at power turnon by the three internal power supplies. 6 Physical Characteristics www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 As long as the RESET terminal is held LOW, the device is in the reset state. During reset, all I2C and serial data bus operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain in that state until device initialization has completed. The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and setting the default register values. Once these are complete, the TAS3108/TAS3108IA enables its master I2C interface and disables its slave I2C interface. Then the TAS3108/TAS3108IA looks for an EEPROM as described in Section 2.6, I 2C Control Interface. 3.4 Power-On Reset (RESET) On power up, it is recommended that the TAS3108/TAS3108IA RESET be held LOW until DVDD has reached 3.3 V. This can be done by programming the system controller or by using an external RC delay circuit. The 1-k and 1-F values provide a delay of approximately 200 s. The values of R and C can be adjusted to provide other delay values as necessary. 3.5 Power Down (PDN) PDN is a user-firmware-definable pin that is programmed in the default TAS3108 and TAS3108IA configuration to stop all clocks in the TAS3108/TAS3108IA, while preserving the state of the device. For more information, see the Texas Instruments document TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067). 3.6 I2C Bus Control (CS0) The TAS3108/TAS3108IA has a control to specify the slave and master I2C address. This control permits up to two TAS3108/TAS3108IA devices to be placed in a system without external logic. See Section 6.2 for a complete description of this pin. 3.7 Programmable I/O (GPIO) The TAS3108/TAS3108IA has one GPIO pin that is 8051 firmware programmable. On power up or following a reset, the GPIO pin becomes an input. Afterwards, the microprocessor can program the GPIO as an input or an output. For more information, see the Texas Instruments document TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067). 3.7.1 No EEPROM is Present or a Memory Error Occurs Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the TAS3108/TAS3108IA is in one of two modes, depending on the setting of the GPIO pin. * GPIO pin is logic HIGH (through a 20-k resistor) With the GPIO pin held HIGH during initialization, the TAS3108/TAS3108IA comes up in the default configuration with the serial data outputs not active. Once the TAS3108/TAS3108IA has completed the default initialization procedure, after the status register is updated and the I2C slave interface is enabled, then the GPIO pin is an output and is driven LOW. Following the HIGH-to-LOW transition of the GPIO pin, the system controller can access the TAS3108/TAS3108IA through the I2C interface and read the status register to determine the load status. If a memory-read error occurs, the TAS3108/TAS3108IA reports the error in the status register (I2C subaddress 0x02). Physical Characteristics 7 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com * GPIO pin is logic LOW (through a 20-k resistor) With GPIO pin held LOW during initialization, the TAS3108/TAS3108IA comes up in an I/O test configuration. In this case, once the TAS3108/TAS3108IA completes its default test initialization procedure, the status register is updated, the I2C slave interface is enabled, and the TAS3108/TAS3108IA streams audio unaltered from input to output as SDIN1 to SDOUT1, SDIN2 to SDOUT2, etc. In this configuration, the GPIO pin is an output signal that is driven LOW. If the external logic is no longer driving the GPIO pin low after the load has completed (~100 ms following a reset if no EEPROM is present), then the state of the GPIO pin can be observed. Then the system controller can access the TAS3108/TAS3108IA through the I2C interface and read the status register to determine the load status. If the GPIO pin state is not observed, the only indication that the device has completed its initialization procedure is the fact that the TAS3108/TAS3108IA streams audio and the I2C slave interface has been enabled. 3.7.2 GPIO Pin Function After Device Is Programmed Once the TAS3108/TAS3108IA has been programmed either through a successful boot load or via slave I2C download, the operation of GPIO can be programmed to be an input and/or output. 3.8 Input and Output Serial Audio Ports The TAS3108/TAS3108IA supports system architectures that require data format conversions between TDM and non-TDM of the same format type without the need for additional glue logic. In addition, the TAS3108/TAS3108IA supports data format conversions between right-justified and I2S and between left-justified and I2S. All the supported conversions are listed in Table 3-1. If the input port is configured for a TDM format, only SDIN1 is active. If a TDM format is selected for the output port, only SDOUT1 is active. Table 3-1. Supported Conversions Input SAP (SDIN1, SDIN2, SDIN3, SDIN4) 2-channel left-justified 2-channel left-justified TDM left-justified 2-channel TDM 2-channel I2S I2S I2S Output SAP (SDOUT1, SDOUT2, SDOUT3, SDOUT4) TDM left-justified 2-channel I2S 2-channel left-justified TDM I2S 2-channel I2S 2-channel left-justified 2-channel right-justified 2-channel I2S 2-channel I2S 2-channel right-justified Table 3-2. Serial Data Input and Output Formats Mode Input Control IM[3:0] 0000 2-channel 0001 0010 Output Control OM[3:0] 0000 0001 0010 Serial Format Left-justified Right-justified I2S Word Lengths 16, 20, 24, 32 16, 20, 24, 32 16, 20, 24 32-192 12.288 Data Rates, kHz MAX SCLK 8 Physical Characteristics www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Table 3-2. Serial Data Input and Output Formats (continued) Mode Input Control IM[3:0] 0011 Time-division multiplexed (4-, 6-, or 8-channel) 0110 0100 0111 0101 1000 Output Control OM[3:0] 0011 0110 0100 0111 0101 1000 Serial Format 8-channel left-justified 8-channel I2S 6-channel left-justified 6-channel I2S 4-channel left-justified 4-channel I2S Word Lengths 16, 20, 24, 32 16, 20, 24 16, 20, 24, 32 16, 20, 24 16, 20, 24, 32 16, 20, 24 Input Port Word Size Data Rates, kHz 32-96 MCLK 32-48 crystal 32-96 32-192 MCLK 32-96 crystal MAX SCLK 24.576 MCLK 12.288 crystal 18.432 24.576 MCLK 12.288 crystal Output Port Word Size 31 S Slave Addr Ack Subaddr Ack 24 Ack 23 xxxxxxxx xxxxxxxx Figure 3-1. Serial Data Controls Table 3-3. Serial Data Input and Output Data Word Sizes IW1, OW1 0 0 1 1 IW0, OW0 0 1 0 1 FORMAT 32-bit data 16-bit data 20-bit data 24-bit data 0x00 15 14 13 XX 11 10 8 IW[2:0] OW[2:0] DWFMT (Data Word Format) 16 Ack 15 8 Ack 7 IOM 0 Ack DWFMT 7 IM[3:0] 4 3 OM[3:0] 0 Input Port Format Output Port Format R0003-01 Physical Characteristics 9 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass updates. Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet operation. However, care must be taken to ensure that the mute command has completed before the SAP is commanded to reconfigure. Similarly, the TAS3108/TAS3108IA should not be commanded to unmute until after the SAP has completed a reconfiguration. The reason for this is that an SAP configuration change while a volume or bass or treble update is taking place can cause the update not to be completed properly. When the TAS3108/TAS3108IA is transmitting serial data, it uses the negative edge of SCLK to output a new data bit. The TAS3108/TAS3108IA samples incoming serial data on the rising edge of SCLK. The TAS3108/TAS3108IA only supports TDM, left-justified, right-justified, and I2S formats. 3.8.1 2-Channel I 2S Timing In 2-channel I2S timing, LRCLK is LOW when left-channel data is transmitted and HIGH when right-channel data is transmitted. SCLK is a bit clock running at 64 x fS which clocks in each bit of the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of the bit clock. The TAS3108/TAS3108IA masks unused trailing data-bit positions. 2-Channel I2S (Philips Format) Stereo Input/Output 32 Clks 32 Clks LRCLK (Note Reversed Phase) Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 20-Bit Mode 19 18 16-Bit Mode 15 14 1 0 5 4 1 0 9 8 5 4 1 0 LSB MSB LSB 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 T0034-04 Figure 3-2. I2S 64-fS Format 10 Physical Characteristics www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 3.8.2 2-Channel Left-Justified In 2-channel left-justified timing, LRCLK is HIGH when left-channel data is transmitted and LOW when right-channel data is transmitted. SCLK is a bit clock running at 64 x fS which clocks in each bit of the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The TAS3108/TAS3108IA masks unused trailing data-bit positions. 2-Channel Left-Justified Stereo Input 32 Clks LRCLK Left Channel LRCLK Right Channel 32 Clks SCLK MSB 24-Bit Mode 23 22 20-Bit Mode 19 18 16-Bit Mode 15 14 1 0 5 4 1 0 9 8 5 4 1 0 LSB MSB LSB 23 22 9 8 5 4 1 0 19 18 5 4 1 0 15 14 1 0 T0034-02 Figure 3-3. Left-Justified 64-fS Format Physical Characteristics 11 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 3.8.3 2-Channel Right-Justified In 2-channel right-justified (RJ) timing, LRCLK is HIGH when left-channel data is transmitted and LOW when right-channel data is transmitted. SCLK is a bit clock running at 64 x fS which clocks in each bit of the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In the RJ mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The data is written MSB-first and is valid on the rising edge of the bit clock. The TAS3108/TAS3108IA masks unused leading data-bit positions. 2-Channel Right-Justified (Sony Format) Stereo Input 32 Clks LRCLK Left Channel Right Channel 32 Clks SCLK MSB 24-Bit Mode 23 22 20-Bit Mode 19 18 16-Bit Mode 15 14 1 15 14 1 19 18 15 14 1 LSB MSB LSB 0 23 22 19 18 15 14 1 0 0 19 18 15 14 1 0 0 15 14 1 0 T0034-03 Figure 3-4. Right-Justified 64-fS Format 3.8.4 TDM Modes The TDM modes on the TAS3108/TAS3108IA provide left-justified and I2S formats. Each word in the TDM data stream adheres to the bit placement shown in Figure 3-5 and Figure 3-6. Two cases are illustrated; an I2S data format case and a left-justified data format case. 12 Physical Characteristics www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 128 Clks LRCLK Left Channels 128 Clks Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC5) 32-Bit Word (DAC7) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 32-Bit Word (DAC6) 32-Bit Word (DAC8) 96 Clks LRCLK Left Channels 96 Clks Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC5) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 32-Bit Word (DAC6) 64 Clks LRCLK Left Channels LRCLK 64 Clks Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 1-Chip, 8-, 6-, 4-Channel and Multiplexed 6-Channel Operation Left-Justified Format SCLK LRCLK MSB 32-Bit Mode 31 30 29 24-Bit Mode 23 22 21 20-Bit Mode 19 18 17 16-Bit Mode 15 14 13 1 0 T0085-01 LSB SCLK 17 16 13 12 9 8 1 0 www 9 8 5 4 1 0 www 3 2 1 0 31 30 29 28 w w w 32 Bit 24 Bit 23 22 21 20 w w w (Example) 5 4 1 0 Figure 3-5. Left-Justified TDM Formats Physical Characteristics 13 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 128 Clks LRCLK Left Channels 128 Clks Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC5) 32-Bit Word (DAC7) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 32-Bit Word (DAC6) 32-Bit Word (DAC8) 96 Clks LRCLK Left Channels 96 Clks Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC5) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 32-Bit Word (DAC6) 64 Clks LRCLK Left Channels LRCLK 64 Clks Right Channels 32-Bit Word (DAC1) 32-Bit Word (DAC3) 32-Bit Word (DAC2) 32-Bit Word (DAC4) 1-Chip, 8-, 6-, 4-Channel and Multiplexed 6-Channel Operation I2S Format SCLK LRCLK MSB 24-Bit Mode 23 22 20-Bit Mode 19 18 16-Bit Mode 15 14 1 0 T0085-02 LSB SCLK 24 Bit 9 8 5 4 1 0 www 5 4 1 0 23 22 21 w w w (Example) Figure 3-6. I2S TDM Formats 14 Physical Characteristics www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 3.8.5 SAP Input to SAP Output--Processing Flow All SAP data format options other than I2S result in a two-sample delay from input to output, as illustrated in Figure 3-7. If I2S formatting is used for both the input SAP and the output SAP, the polarity of LRCLK in Figure 3-7 must be inverted. However, if I2S format conversions are performed between input and output, the delay becomes either 1.5 samples or 2.5 samples, depending on the processing clock frequency selected for the audio DSP core relative to the sample rate of the incoming data. The I2S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core operate on sample windows that are 180 out of phase with respect to the sample window used by the output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint of the sample period used by the audio DSP core to process the data. If the processing cycle completes all processing tasks before the midpoint of the processing sample period, the output SAP outputs this processed data. However, if the processing time extends past the midpoint of the processing sample period, the output SAP outputs the data processed during the previous processing sample period. In the former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output is 2.5 samples. The delay from input to output can thus be either 1.5 or 2.5 sample times when data format conversions are performed that involve the I2S format. However, which delay time is obtained for a particular application is determinable, and fixed for that application, providing care is taken in the selection of MCLKI/XTALI with respect to the incoming sample clock, LRCLK. Physical Characteristics 15 16 1st Half - Sample Time N Sample Time N + 1 Sample Time N Sample Time N + 2 Sample Time N + 1 Sample Time N + 2 2nd Half - Sample Time N Sample Time N Serial Input Rx Holding Regs Regs SDOUT1 U Channel 1 V SDOUT2 W Channel 2 X Input Mux Output Mux Input Holding Regs SDIN1 A Channel 1 B V U Serial Input Rx Holding Regs Regs Input Holding Regs SDOUT1 SDIN1 A TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Physical Characteristics SDOUT2 SDIN2 C Channel 2 D SDOUT3 Y Channel 3 Z F SDIN3 E Channel 3 Z Input Mux Output Mux B SDIN2 C W D X SDOUT3 Y SDIN3 E F SDIN4 G G SDIN4 H H Sample Time N + 1 Sample Time N + 1 Sample Time N + 2 Sample Time N Sample Time N + 2 Sample Time N + 1 Sample Time N + 2 Sample Time N Serial Input Rx Holding Regs Regs SDOUT1 U Channel 1 V SDOUT2 W Channel 2 X Input Mux Output Mux Input Holding Regs SDIN1 Serial Input Rx Holding Regs Regs A Input Holding Regs U Channel 1 B V SDOUT1 Figure 3-7. SAP Input-to-Output Latency SDIN2 C Channel 2 D SDOUT3 Y Channel 3 Z F SDIN3 E Channel 3 Input Mux SDIN1 A B SDOUT2 W Output Mux SDIN2 C D X SDOUT3 Y SDIN3 E F Z SDIN4 G SDIN4 G www.ti.com H H B0076-01 www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 4 Algorithm and Software Development Tools for TAS3108/TAS3108IA The TAS3108/TAS3108IA algorithm and software development tool set is a combination of classical development tools and graphical development tools. The tool set is used to build, debug, and execute programs in both the audio DSP and 8051 sections of the TAS3108/TAS3108IA. Classical development tooling includes text editors, compilers, assemblers, simulators, and source-level debuggers. The 8051 can be programmed exclusively in ANSI C. The 8051 tool set is an off-the-shelf tool set, with modifications as specified in this document. The 8051 tool set is a complete environment with an IDE, editor, compiler, debugger, and simulator. The audio DSP core is programmed exclusively in assembly. The audio DSP tool set is a complete environment with an IDE, context-sensitive editor, assembler, and simulator/debugger. Graphical development tooling provides a means of programming the audio DSP core and 8051 through a graphical drag-and-drop interface using modular audio software components from a component library. The graphical tooling produces audio DSP assembly and 8051 ANSI C code as well as coefficients and data. The classical tools can also be used to produce the executable code. In addition to building applications, the tool set supports the debug and execution of audio DSP and 8051 code on both simulators and EVM hardware. 5 Clock Controls Clock management for the TAS3108/TAS3108IA consists of two control structures: * Master clock management - Oversees the selection of the clock frequencies for the 8051 microprocessor, the I2C controller, and the audio DSP core - The master clock (MCLKI or XTALI) is the source for these clocks. - In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the DPLL output drives the microprocessor and audio DSP clocks. - Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the microprocessor and audio DSP clocks. * Serial audio port (SAP) clock management - Oversees SAP master/slave mode - Controls output of SCLKOUT1, SCLKOUT2, and LRCLK in the SAP master mode Figure 5-2 illustrates the clock circuitry in the TAS3108/TAS3108IA. Input pin MCLKI or XTALI provides the master clock for the TAS3108/TAS3108IA. Within the TAS3108/TAS3108IA, these two inputs are combined by an OR gate, and thus only one of these two sources can be active at any one time. The source that is not active must be logic-0. In normal operation, 1, 2, or 4 (as determined by the logic levels set at input pins PLL0 and PLL1) divides the master clock. The DPLL then multiplies this signal by 11 in frequency (PLL2 = LOW). The multiplier ratio is always 11 (pin PLL2 = LOW). The DPLL output is the processing clock used by the audio DSP core. Algorithm and Software Development Tools for TAS3108/TAS3108IA 17 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com Table 5-1. PLL2, PLL1, and PLL0 Pin Configuration Controls PLL2 0 0 0 0 1 PLL1 0 0 1 1 X PLL0 0 1 0 1 X Audio DSP Clock 11 x MCLK/1 11 x MCLK/2 11 x MCLK/4 Reserved Reserved Audio DSP clock or audio DSP clock/4 is used to clock the on-chip microprocessor. The input pin MICROCLK_DIV makes this clock choice. A logic-1 input level on this pin selects the audio DSP clock for the microprocessor clock; a logic-0 input level on this pin selects the audio DSP clock/4 for the microprocessor clock. The microprocessor clock must be 34 MHz. Table 5-2. MICROCLK_DIV Pin Configuration Control MICROCLK_DIV 0 1 MICROPROCESSOR CLOCK Audio DSP clock/4 Audio DSP clock Note: The state of PLL0, PLL1, PLL2, and MICROCLK_DIV can only be changed while the TAS3108 or TAS3108IA RESET pin is held low. The TAS3108/TAS3108IA only supports dynamic sample-rate changes between any of the supported sample frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the TAS3108/TAS3108IA remains in normal operation and the register contents are preserved. To avoid producing audio artifacts during the sample-rate changes, a volume or mute control can be included in the application firmware that mutes the output signal during the sample-rate change. The fixed-frequency clock can be provided by a crystal, attached to XTLI and XTLO, or an external 3.3-V fixed-frequency TTL source attached to MCLKI. When the TAS3108/TAS3108IA is used in a system in which the master clock frequency (fMCLK) can change, the TAS3108/TAS3108IA must be reset during the frequency change. In these cases, the procedure shown in Figure 5-1 should be used. 18 Clock Controls www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Enable Mute and Wait for Completion RESET Pin = Low Change fMCLK No Are Clocks Stable? Yes RESET Pin = High After TAS3108/TAS3108IA Initializes, Re-initialize I2C Registers F0007-01 Figure 5-1. Master Clock Frequency (fMCLK) Change Procedure Clock Controls 19 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com SCLKIN MCLKI XTALI XTALO MCLKO PLL2 PLL1 PLL0 SCLKOUT1 LRCLK MICROCLK_DIV SCLKOUT2 /2 OSC MCLK /2 M U X M U X /2 / Z = 2DEFAULT /2 M U X M U X PLL x 11 /4 M U X M U X / X = 1DEFAULT /Y = 64DEFAULT M U X PLL and Clock Management Input SAP Audio DSP Core Output SAP Microprocessor and I2C Bus Controller Oversample Clock I2 C Master/Slave Controller N = 0 (Default) 1/2N Master SCL /10 1/(M+1) 8-Bit WARP 8051 Microprocessor M = 8 (Default) 2xSDA 2xSCL B0078-01 Figure 5-2. DPLL and Clock Management Block Diagram When the serial audio port (SAP) is in the master mode, the SAP uses the MCLKI or XTALI master clock to drive the serial port clocks SCLKOUT1, SLCKOUT2, and LRCLK. When the SAP is in the slave mode, LRCLK is an input and SCLKOUT2 and SCLKOUT1 are derived from SCLKIN. As shown in Figure 5-2, SCLKOUT1 clocks data into the input SAP and SCLKOUT2 clocks data from the output SAP. Two distinct clocks are required to support TDM-to-discrete and discrete-to-TDM data-format conversions. Such format conversions also require that SCLKIN be the higher-valued bit-clock frequency. For TDM-in/discrete-out format conversions, SCLKIN must be equal to the input bit clock. For discrete-in/TDM-out format conversions, SCLKIN must be equal to the output bit clock. The frequency settings for SCLKOUT1, SCLKOUT2, and LRCLK in the SAP master mode, as well as the SAP master/slave mode selection, are all controlled by I2C commands. Table 5-3 lists the default settings at power turnon or after a received reset. 20 Clock Controls www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Table 5-3. TAS3108/TAS3108IA Clock Default Settings CLOCK SCLKOUT1 SCLKOUT2 MCLKO LRCLK Audio DSP clock Microprocessor clock PLL multiply ratio I2C sampling clock I2C master SCL DEFAULT SETTING SCLKIN SCLKIN MCLKI or XTALI Input Set by pins PLL0 and PLL1 Set by pin MICROCLK_DIV 11 N=0 M=8 The selections provided by the dedicated TAS3108/TAS3108IA input pins and the programmable settings provided by I2C subaddress commands give the TAS3108/TAS3108IA a variety of clocking options. However, the following clocking restrictions must be adhered to: * MCLKI or XTALI 128 fS (NOTE: For some TDM modes, MCLKI or XTALI must be 256 fS) * Audio DSP clock < 136 MHz * Microprocessor clock/20 I2C SCL clock * Microprocessor clock 34 MHz * I2C oversample clock/20 I2C SCL clock * XTALI 20 MHz * MCLKI 25 MHz As long as these restrictions are met, all other clocking options are allowed. See Clock Register (0x00), Section 7.1, for information on programming the clock register. Clock Controls 21 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com Table 5-4. TAS3108/TAS3108IA MCLK and LRCLK Common Values (MCLK = 12.288 MHz or MCLK = 11.2896 MHz) fS Sample Rate (kHz) Ch per SDIN MCLK/ MCLK Freq LRCLK (MHz) Ratio (x fS) SCLKIN Rate (x fS) SCLKIN Freq (MHz) MCLK/ X Mux 1, 2, SCLK 1, 3, 4, 6, 8, 2, 3, 4, 6, 16, 32 8, 16, 32 SCLK OUT1 Rate (x fS) Ch per SDOUT SCLK OUT2 Rate (x fS) LRCLK fS Rate 32, 64, 128, 192, 256, 384, 512 Input Divider 1, 2, 4 (pins PLL0, PLL1) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PLL Multiplier 11 (pin PLL2) fDSPCLK (MHz) Max 135.2 MHz fDSPCLK/fS Slave Mode, 2 Channels In, 2 Channels Out 32 44.1 48 88.2 96 176.4 192 44.1 48 88.2 96 44.1 48 88.2 96 44.1 48 88.2 96 32 44.1 48 88.2 96 2 2 2 2 2 2 2 2 2 2 2 8 8 4 4 8 8 4 4 2 2 2 2 2 384 256 256 128 128 64 64 256 256 128 128 256 256 128 128 256 256 128 128 384 256 256 128 128 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 12.288 11.2896 12.288 11.2896 12.288 64 64 64 64 64 64 64 256 256 128 128 256 256 128 128 256 256 128 128 N/A N/A N/A N/A N/A 2.048 2.822 3.072 5.645 6.144 11.290 12.288 11.290 12.288 11.290 6.144 11.290 12.288 11.290 12.288 11.290 12.288 11.290 12.288 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 6 4 4 2 2 1 1 1 1 1 1 1 4 4 2 2 4 4 2 2 1 1 1 1 1 1 1 1 1 64 64 64 64 64 64 64 64 64 64 64 256 256 128 128 256 256 128 128 64 64 64 64 64 2 2 2 2 2 2 2 8 8 4 4 2 2 2 2 8 8 4 4 2 2 2 2 2 64 64 64 64 64 64 64 256 256 128 128 64 64 64 64 256 256 128 128 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 256 256 128 128 64 64 64 64 64 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 124.2 135.2 135.2 124.2 135.2 124.2 135.2 4224 2816 2816 1408 1408 704 704 2816 2816 1408 1408 2816 2816 1408 1408 2816 2816 1408 1408 4224 2816 2816 1408 1408 Slave Mode, 2 Channels In, TDM Out Slave Mode, TDM In, 2 Channels Out Slave Mode, TDM In, TDM Out Master Mode, 2 Channels In, 2 Channels Out 22 Clock Controls www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Table 5-4. TAS3108/TAS3108IA MCLK and LRCLK Common Values (MCLK = 12.288 MHz or MCLK = 11.2896 MHz) (continued) fS Sample Rate (kHz) Ch per SDIN MCLK/ MCLK Freq LRCLK (MHz) Ratio (x fS) SCLKIN Rate (x fS) SCLKIN Freq (MHz) MCLK/ X Mux 1, 2, SCLK 1, 3, 4, 6, 8, 2, 3, 4, 6, 16, 32 8, 16, 32 SCLK OUT1 Rate (x fS) Ch per SDOUT SCLK OUT2 Rate (x fS) LRCLK fS Rate 32, 64, 128, 192, 256, 384, 512 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 256 256 128 128 192 128 128 384 Input Divider 1, 2, 4 (pins PLL0, PLL1) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PLL Multiplier 11 (pin PLL2) 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 fDSPCLK (MHz) Max 135.2 MHz fDSPCLK/fS 176.4 192 44.1 48 88.2 96 32 44.1 48 32 44.1 48 88.2 96 32 44.1 48 32 44.1 48 88.2 96 32 44.1 48 32 2 2 2 2 2 2 2 2 2 2 8 8 4 4 6 4 4 4 8 8 4 4 6 4 4 4 64 64 256 256 128 128 384 256 256 384 256 256 128 128 384 256 256 384 256 256 128 128 384 256 256 384 11.2896 12.288 11.2896 12.288 11.2896 12.288 12.288 11.2896 12.288 12.288 11.2896 12.288 11.2896 12.288 12.288 11.2896 12.288 12.288 11.2896 12.288 11.2896 12.288 12.288 11.2896 12.288 12.288 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 1 1 1 1 1 1 2 2 2 3 1 1 1 1 2 2 2 3 1 1 1 1 2 2 2 3 1 1 4 4 2 2 3 2 2 2 4 4 2 2 3 2 2 6 1 1 1 1 1 1 1 1 64 64 64 64 64 64 64 64 64 64 256 256 128 128 192 128 128 384 256 256 128 128 192 128 128 384 2 2 8 8 4 4 6 4 4 4 2 2 2 2 2 2 2 2 8 8 4 4 6 4 4 4 64 64 256 256 128 128 192 128 128 384 64 64 64 64 64 64 64 64 256 256 128 128 192 128 128 384 124.2 135.2 124.2 135.2 124.2 135.2 135.2 124.2 135.2 135.2 124.2 135.2 124.2 135.2 135.2 124.2 135.2 135.2 124.2 135.2 124.2 135.2 135.2 124.2 135.2 135.2 704 704 2816 2816 1408 1408 4224 2816 2816 4224 2816 2816 1408 1408 4224 2816 2816 4224 2816 2816 1408 1408 4224 2816 2816 4224 Master Mode, 2 Channels In, TDM Out Master Mode, TDM In, 2 Channels Out Master Mode, TDM In, TDM Out Clock Controls 23 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 6 Microprocessor Controller The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus controllers the required I2C read data, and participates in most processing tasks requiring multiframe processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I2C commands, a fixed boot-program ROM, and a program RAM. The microprocessor boot program cannot be altered. The microprocessor controller has specialized hardware for master and slave interface operation, volume updates, and a programmable interval timer interrupt. For more information see the TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067). The TAS3108/TAS3108IA has a slave-only I2C interface that is compatible with the Inter IC (I2C) bus protocol and supports both 100-kbps and 400-kbps data-transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes). The slave I2C control interface is used to program the registers of the device and to read device status. The TAS3108/TAS3108IA also has a master-only I2C interface that is compatible with the I2C bus protocol and supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes). The master I2C interface is used to load program and data from an external I2C EEPROM. On power up of the TAS3108/TAS3108IA, the slave interface is disabled and the master interface is enabled. Following a reset, the TAS3108/TAS3108IA disables the slave interface and enables the master interface. Using the master interface, the TAS3108/TAS3108IA automatically tests to see if an I2C EEPROM is at address 1010xxx. The value xxx can be chip select, other information, or don't cares, depending on the EEPROM selected. If a memory is present and it contains the correct header information and one or more blocks of program/memory data, the TAS3108/TAS3108IA loads the program, coefficient, and/or data memories from the EEPROM. If a memory is present, the download is complete when a header is read that has a zero-length data segment. At this point, the TAS3108/TAS3108IA disables the master I2C interface, enables the slave I2C interface, and starts normal operation. If no memory is present or if an error occurred during the EEPROM read, TAS3108/TAS3108IA disables the master I2C interface, enables the slave I2C interface, and loads the unprogrammed default configuration. In this default configuration, the TAS3108/TAS3108IA streams eight channels of audio from input to output if the GPIO pin is LOW. The master and slave interfaces do not operate simultaneously. In the slave mode, the I2C bus is used to: * Load the program and coefficient data - Microprocessor program memory - Microprocessor extended memory - Audio DSP core program memory - Audio DSP core coefficient memory - Audio DSP core data memory * Update coefficient and other control values * Read status flags Once the microprocessor program memory has been loaded, it cannot be updated until the TAS3108/TAS3108IA has been reset. The master and slave modes do not operate simultaneously. When acting as an I2C master, the data transfer rate is fixed at 375 kHz, assuming MCLKI or XTALI = 12.288 MHz, PLL0 = PLL1 = 0, and MICROCLK_DIV = 0. When acting as an I2C slave, the data transfer rate is determined by the master device on the bus. The I2C communication protocol for the I2C slave mode is shown in Figure 6-1. 24 Microprocessor Controller www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Start (By Master) Slave Address (By Master) C S 1 Read or Write (By Master) Data Byte (By Transmitter) C S 0 R / W A C K M S B L S B A C K M S B Data Byte (By Transmitter) L S B Stop (By Master) S 0 1 1 0 1 A C K S (1) Acknowledge (By TAS3108/TAS3108IA) Acknowledge (By Receiver) Acknowledge (By Receiver) SDA SCL Start Condition SDA While SCL = 1 MSB MSB-1 MSB-2 LSB Stop Condition SDA While SCL = 1 T0087-01 Figure 6-1. I C Slave-Mode Communication Protocol 2 6.1 General I2C Operations As shown in Figure 6-2, an I2C read transaction requires that the master device first issue a write transaction to give the TAS3108/TAS3108IA the subaddress to be used in the read transaction that follows. This subaddress assignment write transaction is then followed by the read transaction. For write transactions, the subaddress is supplied in the first byte of data written, and this byte is followed by the data to be written. For I2C write transactions, the subaddress must always be included in the data written. There cannot be a separate write transaction to supply the subaddress, as was required for read transactions. If a subaddress-assignment-only write transaction is followed by a second write transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted by the TAS3108/TAS3108IA as another subaddress replacing the one previously written. Microprocessor Controller 25 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com I2C Read Transaction Start (By Master) Write (By Master) TAS3108/ TAS3108IA Subaddress (By Master) Stop Start (By Master) (By Master) Read (By Master) Data (By TAS3108/ TAS3108IA) Data (By TAS3108/ TAS3108IA) Stop (By Master) S TAS3108/ TAS3108IA Address W ACK Subaddress ACK S S TAS3108/ TAS3108IA Address R ACK Data ACK Data ACK NAK S 7-Bit Slave Address (By Master) Acknowledge (By TAS3108/ TAS3108IA) Acknowledge (By TAS3108/ TAS3108IA) 7-Bit Slave Address (By Master) Acknowledge (By TAS3108/ TAS3108IA) Acknowledge (By Master) Acknowledge (By Master) No Acknowledge (By Master) I2C Write Transaction TAS3108/ TAS3108IA Subaddress (By Master) Start (By Master) Write (By Master) Data (By Master) Data (By Master) Stop (By Master) S TAS3108/ TAS3108IA Address W ACK Subaddress ACK Data ACK Data ACK ACK S 7-Bit Slave Address (By Master) Acknowledge (By TAS3108/ TAS3108IA) Acknowledge (By TAS3108/ TAS3108IA) Acknowledge (By TAS3108/ TAS3108IA) Acknowledge (By TAS3108/ TAS3108IA) Acknowledge (By TAS3108/ TAS3108IA) R0006-01 Figure 6-2. I2C Subaddress Access Protocol 6.2 Detailed I2C Operation The I2C slave mode is the mode that is used to change configuration parameters during operation and to perform program and coefficient downloads from a master device. The latter can be used to replace the I2C master-mode EEPROM download. The TAS3108/TAS3108IA supports both random and sequential I2C transactions. The TAS3108/TAS3108IA I2C slave address is 011010xy, where the first 6 bits are the TAS3108/TAS3108IA device address and bit x is CS0, which is set by the TAS3108/TAS3108IA internal microprocessor at power up. Bit y is the R/W bit. The pulldown resistance of CS0 creates a default 00 address when no connection is made to the pin. Table 6-1 and Table 6-2 show all the legal addresses for I2C slave and master modes. The TAS3108/TAS3108IA I2C block does respond to the broadcast address (00h). Table 6-1. Slave Addresses Base Address 0110 10 0110 10 0110 10 0110 10 CS0 0 0 1 1 R/W 0 1 0 1 Slave Address 0x68 0x69 0x6A 0x6B 26 Microprocessor Controller www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Table 6-2. Master Addresses Base Address 1010 00 1010 00 1010 00 1010 00 CS0 0 0 1 1 R/W 0 1 0 1 Master Address 0xA0 0xA1 0xA2 0xA3 The following is an example use of the I2C master address to access an external EEPROM. The TAS3108/TAS3108IA can address up to two EEPROMs depending on the state of CS0. Initially, the TAS3108/TAS3108IA comes up in I2C master mode. If it finds a memory such as the 24C512 EEPROM, it reads the headers and data as previously described. In this I2C master mode, the TAS3108/TAS3108IA addresses the EEPROMs as shown in Table 6-3 and Table 6-4. Table 6-3. EEPROM Address I2C TAS3108/TAS3108IA Master Mode = 0xA1/A0 MSB 1 0 1 0 0 A0 (EEPROM) 0 CS0 0 R/W 1/0 Table 6-4. EEPROM Address I2C TAS3108/TAS3108IA Master Mode = 0xA3/A2 MSB 1 0 1 0 0 A0 (EEPROM) 0 CS0 1 R/W 1/0 Random I2C Transactions Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. For random I2C read commands, the TAS3108/TAS3108IA responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a given subaddress does not use all 32 bits, the unused bits are read as logic 0. I2C write commands, however, are treated in accordance with the data assignment for that address space. If a write command is received for a biquad subaddress, for example, the TAS3108/TAS3108IA expects to see five 32-bit words. If fewer than five data words have been received when a stop command (or another start command) is received, the data received is discarded. Sequential I2C Transactions The TAS3108/TAS3108IA also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the fifteen subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS3108/TAS3108IA. For I2C sequential write transactions, the subaddress then serves as the start address and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written to. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; just the incomplete data is discarded. Sequential read transactions do not have restrictions on outputting only complete subaddress data sets. If the master does not issue enough data-received acknowledges to receive all the data for a given subaddress, the master device simply does not receive all the data. Microprocessor Controller 27 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com If the master device issues more data-received acknowledges than required to receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending on how many data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both sequential and random, can impose wait states. For the standard I2C mode (SCL = 100 kHz), worst-case wait state time for an 8-MHz microprocessor clock is on the order of 2 s. Nominal wait-state time for the same 8-MHz microprocessor clock is on the order of 1 s. For the fast I2C mode (SCL = 400 kHz) and the same 8-MHz microprocessor clock, worst-case wait-state time can extend up to 10.5 s in duration. Nominal wait-state time for this same case lies in a range from 2 s to 4.6 s. Increasing the microprocessor clock frequency lowers the wait-state time and for the standard I2C mode, a faster microprocessor clock can totally eliminate the presence of wait states. For example, increasing the microprocessor clock to 16 MHz results in no wait states. For the fast I2C mode, faster microprocessor clocks shorten the wait-state time encountered, but do not totally eliminate wait states. 6.2.1 Multiple-Byte Write Multiple data bytes are transmitted by the master device to slave as shown in Figure 6-3. After receiving each data byte, the TAS3108/TAS3108IA responds with an acknowledge bit. Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A3 A1 A0 ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK I2C Device Address and Read/Write Bit Subaddress First Data Byte Other Data Bytes Last Data Byte Stop Condition T0036-02 Figure 6-3. Multiple-Byte Write Transfer 6.2.2 Multiple-Byte Read Multiple data bytes are transmitted by the TAS3108/TAS3108IA to the master device as shown in Figure 6-4. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Not Acknowledge A6 A0 R/W ACK A7 A6 A5 A0 ACK A6 A0 R/W ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK I2C Device Address and Read/Write Bit Subaddress I2C Device Address and Read/Write Bit First Data Byte Other Data Bytes Last Data Byte Stop Condition T0036-04 Figure 6-4. Multiple-Byte Read Transfer 6.3 I2C Master-Mode Device Initialization I2C master-mode operation is enabled following a reset or power-on reset. Master-mode I2C transactions do not start until the I2C bus is idle. The TAS3108/TAS3108IA uses the master mode to download from EEPROM the memory contents for the microprocessor program memory, microprocessor extended memory, audio DSP core program memory, audio DSP core coefficient memory, and audio DSP core data memory. 28 Microprocessor Controller www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 The TAS3108/TAS3108IA, when operating as an I2C master, can execute a complete download of any internal memory or any section of any internal memory without requiring any wait states. When the TAS3108/TAS3108IA operates as an I2C master, the TAS3108/TAS3108IA generates a repeated start without an intervening stop command while downloading program and memory data from EEPROM. When a repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to transfer large blocks of data quickly. The TAS3108/TAS3108IA queries the bus for an I2C EEPROM at address 1010xxx. The value xxx can be chip select, other information, or don't cares, depending on the EEPROM selected. The first action of the TAS3108/TAS3108IA as master is to transmit a start condition along with the device address of the I2C EEPROM with the read/write bit cleared (0) to indicate a write. The EEPROM acknowledges the address byte, and the TAS3108/TAS3108IA sends a subaddress byte, which the EEPROM acknowledges. Most EEPROMs have at least 2-byte addresses and acknowledge as many as are appropriate. At this point, the EEPROM sends a last acknowledge and becomes a slave transmitter. The TAS3108/TAS3108IA acknowledges each byte repeatedly to continue reading each data byte that is stored in memory. The memory load information starts with reading the header and data information that starts at subaddress 0 of the EEPROM. This information must then be stored in sequential memory addresses with no intervening gaps. The data blocks are contiguous blocks of data that immediately follow the header locations. The TAS3108/TAS3108IA memory data can be stored and loaded in (almost) any order. Additionally, this addressing scheme permits portions of the TAS3108/TAS3108IA internal memories to be loaded. I2C EEPROM Memory Map Block Header 1 Data Block 1 Block Header 2 Data Block 2 w w w Block Header N Data Block N M0040-01 Figure 6-5. EEPROM Address Map The TAS3108/TAS3108IA sequentially reads EEPROM memory and loads its internal memory unless it does not find a valid memory header block, is not able to read the next memory location because the end Microprocessor Controller 29 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com of memory was reached, detects a checksum error, or reads an end-of-program header block. When it encounters an invalid header or read error, the TAS3108/TAS3108IA attempts to read the header or memory location three times before it determines that it has an error. If the TAS3108/TAS3108IA encounters a checksum error it attempts to re-read the entire block of memory two more times before it determines that it has an error. Once the microprocessor program memory has been loaded, it cannot be reloaded until the TAS3108/TAS3108IA has been reset. If an error is encountered, TAS3108/TAS3108IA terminates its memory-load operation, loads the default configuration, and disables further master I2C bus operations. If an end-of-program data block is read, the TAS3108/TAS3108IA has completed the initial program load. The I2C master mode uses the starting and ending I2C checksums to verify a proper EEPROM download. The first 16-bit data word received from the EEPROM, the I2C checksum at subaddress 0x00, is stored and compared against the 16-bit data word received for the last subaddress, the ending I2C checksum, and the checksum that is computed during the download. These three values must be equal. If the read and computed values do not match, the TAS3108/TAS3108IA sets the memory read error bits in the status register and repeats the download from the EEPROM two more times. If the comparison check fails the third time, the TAS3108/TAS3108IA sets the microprocessor program to the default value. Table 6-5 shows the format of the EEPROM or other external memory load file. Each line of the file is a byte (in ASCII format). The checksum is the summation of all the bytes (with beginning and ending checksum fields = 00). The final checksum inserted into the checksum field is the lowest significant four bytes of the checksum. Example: Given the following example 8051 data or program block (must be a multiple of 4 bytes for these blocks): 10h 20h 30h 40h 50h 60h 70h 80h The checksum = 10h + 20h + 30h + 30h + 40h + 50h + 60h + 70h + 80h = 240h, so the values put in the checksum fields are MS byte = 02h and LS byte = 40h. If the checksum is > FFFFh, then the 2-byte checksum field is the least-significant 2 bytes. For example, if the checksum is 1D 45B6h, then the checksum field is MS byte = 45h and LS byte = B6h. Table 6-5. TAS3108/TAS3108IA Memory Block Structures STARTING BYTE 0 DATA BLOCK FORMAT SIZE 12-Byte Header Block Checksum code MS byte Checksum code LS byte 2 bytes Checksum of bytes 2 through N + 12 NOTES 30 Microprocessor Controller www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Table 6-5. TAS3108/TAS3108IA Memory Block Structures (continued) STARTING BYTE 2 4 DATA BLOCK FORMAT Header ID byte 1 = 0x00 Header ID byte 2 = 0x1F Memory to be loaded 1 byte 0x00 Microprocessor program memory or termination header 0x01 Microprocessor external data memory 0x02 Audio DSP core program memory 0x03 Audio DSP core coefficient memory 0x04 Audio DSP core data memory 0x05-0x0F Reserved for future expansion Unused If this is a termination header, this value is 0000. SIZE 2 bytes NOTES Must be 0x001F for the TAS3108/TAS3108IA to load 5 6 0x00 Start TAS3108/TAS3108IA memory address MS byte Start TAS3108/TAS3108IA memory address LS byte 1 byte 2 bytes 8 10 11 12 Total number of bytes transferred MS byte Total number of bytes transferred LS byte 0x00 0x00 Data byte 1 (LS byte) Data byte 2 Data byte 3 Data byte 4 (MS byte) 2 bytes 1 bytes 1 bytes 4 bytes 12 + data bytes + last checksum bytes. If this is a termination header, this value is 0000. Unused Unused 1-4 microprocessor bytes Data Block for Microprocessor Program or Data Memory (Following 12-Byte Header) 16 Data byte 5 Data byte 6 Data byte 7 Data byte 8 * * * 4 bytes 5-8 microprocessor bytes N+8 Data byte 4*(Z - 1) + 1 Data byte 4*(Z - 1) + 2 Data byte 4*(Z - 1) + 3 Data byte 4*(Z - 1) + 4 = N 4 bytes N + 12 0x00 0x00 Checksum code MS byte Checksum code LS byte 4 bytes Repeated checksum bytes 2 through N + 11 Data Block for Audio DSP Core Coefficient Memory (Following 12-Byte Header) 12 Data byte 1 (LS byte) Data byte 2 Data byte 3 Data byte 4 (MS byte) 16 Data byte 5 Data byte 6 Data byte 7 Data byte 8 * * Microprocessor Controller 31 4 bytes 4 bytes Coefficient word 1 (valid data in D27-D0) D7-D0 D15-D8 D23-D16 D31-D24 Coefficient word 2 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com Table 6-5. TAS3108/TAS3108IA Memory Block Structures (continued) STARTING BYTE N+8 DATA BLOCK FORMAT * Data byte 4*(Z - 1) + 1 Data byte 4*(Z - 1) + 2 Data byte 4*(Z - 1) + 3 Data byte 4*(Z - 1) + 4 = N N + 12 0x00 0x00 Checksum code MS byte Checksum code LS byte Data Block for Audio DSP Core Data Memory (Following 12-Byte Header) 12 Data byte 1 (LS byte) Data byte 2 Data byte 3 Data byte 4 Data byte 5 Data byte 6 (MS byte) 18 Data byte 7 Data byte 8 Data byte 9 Data byte 10 Data byte 11 Data byte 12 * * * N+6 Data byte 6*(Z - 1) + 1 Data byte 6*(Z - 1) + 2 Data byte 6*(Z - 1) + 3 Data byte 6*(Z - 1) + 4 Data byte 6*(Z - 1) + 5 Data byte 6*(Z - 1) + 6 = N N + 12 0x00 0x00 0x00 0x00 Checksum code MS byte Checksum code LS byte Data Block for Audio DSP Core Program Memory (Following 12-Byte Header) 12 Program byte 1 (LS byte) Program byte 2 Program byte 3 Program byte 4 Program byte 5 Program byte 6 Program byte 7 (MS byte) 7 bytes Program word 1 (valid data in D53-D0) D7-D0 D15-D8 D23-D16 D31-D24 D39-D32 D47-D40 D55-D48 6 bytes Repeated checksum bytes 2 through N + 11 6 bytes Data Z 6 bytes 6 bytes Data word 1 D7-D0 D15-D8 D23-D16 D31-D24 D39-D32 D47-D40 Data 2 4 bytes Repeated checksum bytes 2 through N + 11 4 bytes Coefficient word Z SIZE NOTES 32 Microprocessor Controller www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 Table 6-5. TAS3108/TAS3108IA Memory Block Structures (continued) STARTING BYTE 19 DATA BLOCK FORMAT Program byte 8 Program byte 9 Program byte 10 Program byte 11 Program byte 12 Program byte 14 Program byte 15 * * * N+5 Program byte 7*(Z - 1) + 1 Program byte 7*(Z - 1) + 2 Program byte 7*(Z - 1) + 3 Program byte 7*(Z - 1) + 4 Program byte 7*(Z - 1) + 5 Program byte 7*(Z - 1) + 6 Program byte 7*(Z - 1) + 7 = N N + 12 0x00 0x00 0x00 0x00 0x00 Checksum code MS byte Checksum code LS byte 20-Byte Termination Block (Last Block of Entire Load Block) BLAST - 19 BLAST - 17 BLAST - 15 BLAST - 14 BLAST 0x00 0x00 0x00 0x1F 0x00 0x00 * 0x00 1 byte 1 byte 1 byte Last 16 bytes must each be 0x00. 2 bytes Second 2 bytes are always 0x001F. 2 bytes First 2 bytes of termination block are always 0x0000. 7 bytes Repeated checksum bytes 2 through N + 11 7 bytes Program word Z SIZE 7 bytes Program word 2 NOTES Microprocessor Controller 33 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 7 I2C Register Map SUBADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A * * * 0xFE 0xFF User-defined User-defined 4, 8, 12, 16, or 20 4, 8, 12, 16, or 20 REGISTER NAME Clock and SAP control register Reserved Status register Unused I2C memory load control register I2C memory load data register PEEK/POKE address PEEK/POKE data Version number User-defined User-defined 8 8 4 16 4 4, 8, 12, 16, or 20 4, 8, 12, 16, or 20 Description shown in Section 7.3 Description shown in Section 7.3 u(31:24) (1), MemSelect(23:16), Addr(15:8), Addr(7:0) D(63:56), D(55:48), D(47:40), D(39:32), D(31:24), D(23:16), D(15:8), D(7:0) TAS3108/TAS3108IA version User-defined register 1 User-defined register 2 * * * User-defined register 246 User-defined register 247 User-defined User-defined 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x01 User-defined User-defined NO. OF BYTES 4 4 4 CONTENTS Description shown in Section 7.1 Reserved Description shown in Section 7.2 INITIALIZATION VALUE 0x01, 0x00, 0x1B, 0x22 0x00, 0x00, 0x00, 0x40 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 (1) u indicates unused bits. In the following sections, BOLD indicates the default state of the bit fields. 34 I2C Register Map www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 7.1 Clock Control Register (0x00) Register 0x00 provides the user with control over MCLK, LRCLK, SCLKOUT1, SCLKOUT2, data-word size, and serial audio port modes. Register 0x00 default = 0x0100 1B22. Table 7-1. Clock Control Register (0x00) D31 0 D30 0 D29 0 D28 W1 D27 W0 D26 D25 D24 Not Used Master clock output divider DESCRIPTION Y2 D23 ICS IMS X2 X1 X0 Z2 D15 X D14 X X IW1 IW0 X D13 D12 D11 D10 D22 D21 D20 D19 D18 Y1 D17 Y0 D16 Master mode LRCLK divider DESCRIPTION SCLKOUT select (default = 0) SAP master/slave mux select (1 = master mode, 0 = slave mode) SCLKIN and SCLKOUT clock divide Z1 D9 Z0 D8 MCLK, SCLK ratio (master mode only) DESCRIPTION Don't care Don't care Input audio data word size Don't care OW1 D7 IM3 D6 IM2 D5 IM1 D4 IM0 OM3 OM2 OM1 D3 D2 D1 OW0 D0 Output audio data word size DESCRIPTION Input data format Output data format OM0 7.1.1 Master Clock Output Divider Bits 28-27 (W1 and W0) define the ratio between MCLKI (or the crystal frequency) and MCLKO. This allows the accommodation of devices that require an MCLK = 128 LRCLK and devices that require an MCLK = 256 LRCLK, without having to use glue logic to divide that clock down. This bit has meaning whether in clock-master or clock-slave mode. W1 0 0 1 1 W0 0 1 0 1 MCLKO = MCLKI MCLKO = MCLKI/2 MCLKO = MCLKI/4 MCLKO = MCLKI/4 DESCRIPTION I2C Register Map 35 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 7.1.2 Master Mode LRCLK Divider Bits 26-24 (Y2, Y1, and Y0) define the ratio between SCLK and LRCLK, but only have meaning in the clock-master mode where LRCLK is an output. In the clock-slave mode, LRCLK is an input. Y2 0 0 0 0 1 1 1 1 Y1 0 0 1 1 0 0 1 1 Y0 0 1 0 1 0 1 0 1 LRCLK out = SCLK/32 LRCLK out = SCLK/64 LRCLK out = SCLK/128 LRCLK out = SCLK/192 LRCLK out = SCLK/256 LRCLK out = SCLK/384 LRCLK out = SCLK/512 LRCLK out = SCLK/32 DESCRIPTION 7.1.3 SCLKIN and SCLKOUT Clock Divide Bits 21-19 (X2, X1, and X0) define the ratio between SCLKIN and SCLKOUT. These control bits are only used when the input and output rates are different, which can happen if TDM and discrete modes are both used (for example, input is TDM and output is discrete). Normally, these bits are set to 000, so that SCLKOUT1 (input SCLK) and SLCKOUT2 (output SCLK) are the same. (Note that SCLKIN is not the input SCLK, but is used in clock-slave mode to derive SCLKOUT1.) X2 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 X MUX out = IMS_MUX/2 X MUX out = IMS_MUX/3 X MUX out = IMS_MUX/4 X MUX out = IMS_MUX/6 X MUX out = IMS_MUX/8 X MUX out = IMS_MUX/16 X MUX out = IMS_MUX/32 DESCRIPTION X MUX out = IMS_MUX (master/slave SCLK) 7.1.4 MCLK, SCLK Ratio (Master Mode Only) Bits 18-16 (Z2, Z1, and Z0) define the ratio between MCLK and SCLK when the TAS3108/TAS3108IA is the clock master. In clock-slave mode, these bits are don't care. Z2 0 0 0 0 1 1 1 1 Z1 0 0 1 1 0 0 1 1 Z0 0 1 0 1 0 1 0 1 Z MUX out = MCLK/2 Z MUX out = MCLK/3 Z MUX out = MCLK/4 Z MUX out = MCLK/6 Z MUX out = MCLK/8 Z MUX out = MCLK/16 Z MUX out = MCLK/32 DESCRIPTION Z MUX out = MCLK (MCLKI or crystal oscillator) 36 I2C Register Map www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 7.1.5 Audio Data Word Size Bits 12-11 (IW1 and IW0) define the data word size for the input SAP. Bits 9-8 (OW1 and OW0) define the data word size for the output SAP. IW1/OW1 0 0 1 1 IW0/OW0 0 1 0 1 32-bit audio data 16-bit audio data 20-bit audio data 24-bit audio data DESCRIPTION 7.1.6 Input and Output Data Format Bits 7-4 (IM3, IM2, IM1, and IM0) define the input data format. Bits 3-0 (OM3, OM2, OM1, and OM0) define the output data format. The two formats need not be the same, only compatible. IM3/OM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IM2/OM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IM1/OM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IM0/OM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2-channel, left-justified 2-channel, right-justified 2-channel, I2S TDM, left-justified (8 channels) TDM, left-justified (6 channels) TDM, left-justified (4 channels) TDM, I2S (8 channels) TDM, I2S (6 channels) TDM, I2S (4 channels) 2-channel, I2S 2-channel, I2S 2-channel, I2S 2-channel, I2S 2-channel, I2S 2-channel, I2S 2-channel, I2S DESCRIPTION I2C Register Map 37 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 7.2 Status Register (0x02) During I2C download, the write operation to indicate that a particular memory is to be written causes the TAS3108/TAS3108IA to set an error bit to indicate a load for that memory type. This error bit is cleared when the operation completes successfully. Table 7-2. Status Register (0x02) D31 - D23 - D15 D30 - D22 - D14 D29 - D21 - D13 D28 - D20 - D12 D27 - D19 - D11 D26 - D18 - D10 D25 - D17 - D9 D24 - D16 - D8 Firmware definable Firmware definable Firmware definable DESCRIPTION DESCRIPTION DESCRIPTION D7 0 0 0 0 0 0 1 1 0 D6 0 0 0 0 0 0 1 1 0 D5 - - - - - 1 1 1 0 D4 - - - - 1 - 1 1 0 D3 - - - 1 - - 0 1 0 D2 - - 1 - - - 0 1 0 D1 - 1 - - - - 0 1 0 D0 1 - - - - - 0 1 0 DESCRIPTION Microprocessor program memory load error Microprocessor external data memory load error Audio DSP core program memory load error Audio DSP core coefficient memory load error Audio DSP core data memory load error Invalid memory select End-of-load header error No EPROM present No errors 38 I2C Register Map www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 7.3 I2C Memory Load Control and Data Registers (0x04 and 0x05) Registers 0x04 (Table 7-3) and 0x05 (Table 7-4) allow the user to download TAS3108/TAS3108IA program code and data directly from the system I2C controller. This mode is called the I2C slave mode (from the TAS3108/TAS3108IA point-of-view). See the TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details. Table 7-3. TAS3108/TAS3108IA Memory Load Control Register (0x04) BYTE 1-2 3-4 DATA BLOCK FORMAT Checksum code Memory to be loaded SIZE 2 bytes 2 bytes NOTES Checksum of bytes 2 through N + 8. If this is a termination header, this value is 0000. 0 Microprocessor program memory 1 Microprocessor external data memory 2 Audio DSP core program memory 3 Audio DSP core coefficient memory 4 Audio DSP core data memory 5-15 Reserved for future expansion Reserved for future expansion If this is a termination header - this value is 0000. If this is a termination header - this value is 0000. 5 6-7 7-8 Unused Starting TAS3108/TAS3108IA memory address Number of data bytes to be transferred 1 byte 2 bytes 2 bytes Table 7-4. TAS3108/TAS3108IA Memory Load Data Register (0x05) BYTE 1 2 3 4 5 6 7 8 8-BIT DATA Datum 1 D7-D0 Datum 2 D7-D0 Datum 3 D7-D0 Datum 4 D7-D0 Datum 5 D7-D0 Datum 6 D7-D0 Datum 7 D7-D0 Datum 8 D7-D0 28-BIT DATA 0000 D27-D24 D7-D0 D15-D8 D7-D0 0000 D27-D24 D23-D16 D15-D8 D7-D0 48-BIT DATA 0000 0000 0000 0000 D47-D40 D39-D32 D31-D24 D23-D16 D15-D8 D7-D0 54-BIT DATA 0000 0000 00 D53-D48 D47-D40 D39-D32 D31-D24 D23-D16 D15-D8 D7-D0 I2C Register Map 39 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 7.4 Memory Access Registers (0x06 and 0x07) Registers 0x06 (Table 7-5) and 0x07 (Table 7-6) allow the user to access the internal resources of the TAS3108/TAS3108IA. See TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) for more details. Table 7-5. Memory Select and Address Register (0x06) D31 - D23 0 0 0 0 0 0 0 0 D15 A0 D7 A8 D30 - D22 0 0 0 0 0 0 0 0 D14 A1 D6 A9 D29 - D21 0 0 0 0 0 0 0 0 D13 A2 D5 A10 D28 - D20 0 0 0 0 0 0 0 0 D12 A3 D4 A11 D27 - D19 0 0 0 0 0 0 0 1 D11 A4 D3 A12 D26 - D18 0 0 0 1 1 1 1 0 D10 A5 D2 A13 D25 - D17 0 1 1 0 0 1 1 0 D9 A6 D1 A14 D24 - D16 1 0 1 0 1 0 1 0 D8 A7 D0 A15 Memory address Memory address Unused DESCRIPTION DESCRIPTION Audio DSP core coefficient memory select Audio DSP core data memory select Reserved Microprocessor internal data memory select Microprocessor external data memory select SFR select Microprocessor program RAM select Audio DSP core program RAM select DESCRIPTION DESCRIPTION Table 7-6. Data Register (Peek and Poke) (0x07) D63 D63 D55 D55 D47 D47 D39 D39 D31 D31 D23 D23 D15 D15 D7 D7 D62 D62 D54 D54 D46 D46 D38 D38 D30 D30 D22 D22 D14 D14 D6 D6 D61 D61 D53 D53 D45 D45 D37 D37 D29 D29 D21 D21 D13 D13 D5 D5 D60 D60 D52 D52 D44 D44 D36 D36 D28 D28 D20 D20 D12 D12 D4 D4 D59 D59 D51 D51 D43 D43 D35 D35 D27 D27 D19 D19 D11 D11 D3 D3 D58 D58 D50 D50 D42 D42 D34 D34 D26 D25 D18 D18 D10 D10 D2 D2 D57 D57 D49 D49 D41 D41 D33 D33 D25 D26 D17 D17 D9 D9 D1 D1 D56 D56 D48 D48 D40 D40 D32 D32 D24 D25 D16 D16 D8 D8 D0 D0 Data to be written or read Data to be written or read DESCRIPTION Data to be written or read DESCRIPTION Data to be written or read DESCRIPTION Data to be written or read DESCRIPTION Data to be written or read DESCRIPTION Data to be written or read DESCRIPTION Data to be written or read DESCRIPTION DESCRIPTION 40 I2C Register Map www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 8 8.1 Electrical Specifications Absolute Maximum Ratings Over Operating Temperature Range (unless otherwise noted) (1) Supply voltage range, DVDD Supply voltage, AVDD 3.3-V TTL 1.8 V LVCMOS (XTLI) 3.3 V TTL 1.8 V LVCMOS (XTLO) -0.5 V to 3.8 V -0.5 V to 3.8 V -0.5 V to DVDD + 0.5 V -0.5 V to 2.3 V -0.5 V to DVDD + 0.5 V -0.5 V to 2.3V (2) 20 A 20 A 0C to 70C -40C to 105C -65C to 150C VI VO IIK IOK TA Tstg (1) (2) Input voltage range Output voltage range Input clamp current (VI < 0 or VI > DVDD Output clamp current (VO < 0 or VO > DVDD) TAS3108 operating free-air temperature TAS3108IA operating free-air temperature Storage temperature range Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Pin XTALO is the only TAS3108/TAS3108IA output that is derived from the internal 1.8-V logic supply. The absolute maximum rating listed is for reference; only a crystal should be connected to XTALO. 8.2 Package Dissipation Ratings (TAS3108/TAS3108IA) Package Description Pkg Type TSSOP Pin Count 38 Package Designator DCP TAS3108IA (Use 2 oz. Trace and Thermal Pad With Solder) JA (C/W) 27.41 JC (C/W) 0.72 TAS3108 (Use 2 oz. Trace and Thermal Pad Without Solder ) JA (C/W) 52.93 JC (C/W) 0.72 See Application Information, Section 9, for PCB recommendations for TAS3108IA applications. 8.3 Recommended Operating Conditions (TAS3108/TAS3108IA) MIN Digital supply voltage, DVDD 3 3.3 V TTL 1.8 V LVCMOS (XTL_IN) 3.3 V TTL 1.8 V LVCMOS (XTL_IN) TAS3108 TAS3108IA TAS3108 TAS3108IA 0 -40 0 -40 25 25 2 1.2 0.8 0.5 70 105 105 125 NOM 3.3 MAX 3.6 UNIT V V V C C VIH VIL TA TJ High-level input voltage Low-level input voltage Operating ambient air temperature range Operating junction temperature range Electrical Specifications 41 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 8.4 Electrical Characteristics (TAS3108/TAS3108IA) PARAMETER 3.3-V TTL TEST CONDITIONS IOH = -4 mA IOH = -0.55 mA IOL = 4 mA IOL = 0.75 mA VI = VIL VI = VIL VI = VIL VI = VIH VI = VIH MCLKI = 24.576 MHz, LRCLK = 192 kHz 110 100 70 16 3 2 mA mA mA mA MIN 2.4 1.44 0.5 0.4 20 1 1 1 1 V A A A V TYP MAX UNIT over recommended operating conditions (unless otherwise noted) VOH High-level output voltage 1.8-V LVCMOS (XTL_OUT) 3.3-V TTL 1.8-V LVCMOS (XTL_OUT) 3.3-V TTL 3.3-V TTL 1.8-V LVCMOS (XTL_IN) 3.3-V TTL 1.8-V LVCMOS (XTL_IN) VOL Low-level output voltage High-impedance output current Low-level input current High-level input current IOZ IIL IIH IDVDD Digital supply current Normal operation MCLKI = 12.288 MHz, LRCLK = 48 kHz MCLKI = 8.192 MHz, LRCLK = 32 kHz Power down enabled IA_DVDD Analog supply current Normal operation Power down enabled LRCLK, SCLK, MCLKI running MCLKI = 24.576 MHz, LRCLK = 192 kHz LRCLK, SCLK, MCLKI running 42 Electrical Specifications www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 8.5 Timing Characteristics The following sections describe the timing characteristics of the TAS3108/TAS3108IA. 8.5.1 Master Clock Signals (TAS3108/TAS3108IA) PARAMETER TEST CONDITIONS See (1) over recommended operating conditions (unless otherwise noted) MIN 6 50 6 See (2) TYP MAX 20 166 25 UNIT MHz ns MHz ns ns MHz ns ns ns ps ps f(XTALI) tc(1) f(MCLKI) tw(MCLKI) f(MCLKO) tr(MCLKO) tf(MCLKO) tw(MCLKI) Frequency, XTALI (1/ tc(1)) Cycle time, XTALI Frequency, MCLKI (1/ tc(2)) Pulse duration, MCLKI high MCLKI jitter Frequency, MCLKO (1/ tc(3)) Rise time, MCLKO Fall time, MCLKO Pulse duration, MCLKO high MCLKO jitter XTALI master clock source 0.4 tc(2) 6 0.5 tc(2) 0.6 tc(2) 5 25 15 15 CL = 30 pF CL = 30 pF See (3) HMCLKO 80 MCLKI master clock source See See See (4) (5) (5) (6) td(MI-MO) (1) (2) (3) (4) (5) (6) Delay time, MCLKI rising MCLKO = MCLKI edge to MCLKO rising MCLKO < MCLKI edge 20 20 ns ns Duty cycle is 50/50. Period of MCLKI = TMCLKI = 1 / fMCLKI HMCLKO = 1/(2 x MCLKO). MCLKO has the same duty cycle as MCLKI when MCLKO = MCLKI. When MCLKO = 0.5 MCLKI or 0.25 MCLKI, the duty cycle of MCLKO is typically 50%. When MCLKO is derived from MCLKI, MCLKO jitter = MCLKI jitter Only applies when MCLKI is selected as master source clock Also applies to MCLKO falling edge when MCLKO = MCLKI/2 or MCLKI/4. XTALI tc(1) tw(MCLKI) MCLKI tc(2) tw(MCLKO) tf(MCLKO) MCLKO tc(3) T0088-01 td(MI-MO) tr(MCLKO) Figure 8-1. Master Clock Signal Timing Waveforms Electrical Specifications 43 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 8.5.2 Serial Audio Port Slave Mode Signals (TAS3108/TAS3108IA) PARAMETER TEST CONDITIONS See See (1) (2) over recommended operating conditions (unless otherwise noted) MIN 32 0.4 tc(SCLKIN) 64 fS 10 0.5 tc(SCLKIN) 10 10 17 0.5 tc(SCLKIN) TYP MAX 192 0.6 tc(SCLKIN) 25 15 UNIT kHz ns MHz ns ns ns ns ns ns fLRCLK fSCLKIN tpd1 tsu1 th1 tsu2 th2 tpd2 (1) (2) Frequency, LRCLK (fS) Frequency, SCLKIN Propagation delay, SCLKIN falling edge to SDOUT Setup time, LRCLK to SCLKIN rising edge Hold time, LRCLK from SCLKIN rising edge Setup time, SDIN to SCLKIN rising edge Hold time, SDIN from SCLKIN rising edge Propagation delay, SCLKIN falling edge to SCLKOUT2 falling edge tw(SCLKIN) Pulse duration, SCLKIN high Period of SCLKIN = TSCLKIN = 1/fSCLKIN Duty cycle is 50/50. tw(SCLKIN) tc(SCLKIN) SCLKIN th1 tsu1 LRCLK (Input) tpd1 SDOUT1 SDOUT2 SDOUT3 SDOUT4 th2 tsu2 SDIN1 SDIN2 SDIN3 SDIN4 tpd2 SCLKOUT2 T0090-01 Figure 8-2. Serial Audio Port Slave Mode Timing Waveforms 44 Electrical Specifications www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 8.5.3 Serial Audio Port Master Mode Signals (TAS3108/TAS3108IA) PARAMETER TEST CONDITIONS CL = 30 pF (1) over recommended operating conditions (unless otherwise noted) MIN 32 TYP MAX 192 12 12 64 fS 25 20 20 4 4 4 20 23 3 UNIT kHz ns ns MHz ns ns ns ns ns ns ns ns f(LRCLK) tr(LRCLK) tf(LRCLK) f(SCLKOUT) tr(SCLKOUT) tf(SCLKOUT) tpd1(SCLKOUT1) tpd1(SCLKOUT2) tpd2 tsu th t(SKEW) (1) Frequency LRCLK Rise time, LRCLK Fall time, LRCLK (1) CL = 30 pF Duty cycle is 50/50. CL = 30 pF CL = 30 pF CL = 30 pF Frequency, SCLKOUT1/SCLKOUT2 Rise time, SCLKOUT1/SCLKOUT2 Fall time, SCLKOUT1/SCLKOUT2 Propagation delay, SCLKOUT1 falling edge to LRCLK edge Propagation delay, SCLKOUT2 falling edge to LRCLK edge Propagation delay, SCLKOUT2 falling edge to SDOUT Setup time, SDIN to SCLKOUT1 rising edge Hold time, SDIN from SCLKOUT1 rising edge Skew time, SCLKOUT1 to SCLKOUT2 Rise time and fall time measured from 20% to 80% of maximum height of waveform. tr(SCLKOUT) tf(SCLKOUT) SCLKOUT2 tr(SCLKOUT) tf(SCLKOUT) SCLKOUT1 tpd1(SCLKOUT2) tpd1(SCLKOUT1) LRCLK (Output) tf(LRCLK), tr(LRCLK) SDOUT1 SDOUT2 SDOUT3 SDOUT4 tpd2 tsk th tsu SDIN1 SDIN2 SDIN3 SDIN4 T0091-01 Figure 8-3. TAS3108/TAS3108IA Serial Audio Port Master Mode Timing Waveforms Electrical Specifications 45 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 8.5.4 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices PARAMETER VIL VIH Vhys VOL1 tof II tSP(SCL) tSP(SDA) CI (1) (2) (3) LOW-level input voltage HIGH-level input voltage Hysteresis of inputs LOW-level output voltage (open drain or open collector) Output fall time from VIHmin to VILmax Input current, each I/O pin SCL pulse duration of spikes which must be suppressed by the input filter SDA pulse duration of spikes which must be suppressed by the input filter Capacitance, each I/O pin I2C 3-mA sink current Bus capacitance from 10 pF to 400 pF -10 N/A N/A TEST CONDITIONS STANDARD MODE MIN -0.5 2 N/A N/A MAX 0.8 FAST MODE MIN -0.5 2 0.05 VDD 0 250 7 + 0.1 Cb (1) 10 N/A N/A 10 -10 (2) 14 (3) 22 (3) 10 0.4 250 10 (2) MAX 0.8 UNIT V V V V ns A ns ns pF Cb = capacitance of one bus line in pF. The output fall time is faster than the standard specification. The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off. These values are valid at the 135-MHz DSP clock rate. If DSP clock is reduced by half, the tSP doubles. NOTE SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges of SCL. 46 Electrical Specifications www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 8.5.5 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices A All values are referred to VIHmin and VILmax (see Section 8.5.4). STANDARD MODE MIN 0 4 4.7 4 4.7 250 0 3.45 300 20 + 0.1 Cb 4 4.7 400 0.1 VDVDD 0.2 VDVDD 0.1 VDVDD 0.2 VDVDD MAX 100 FAST MODE MIN 0 0.6 1.3 0.6 0.6 100 0 (4) PARAMETER fSCL tHD-STA tLOW tHIGH tSU-STA tSU-DAT tHD-DAT tr tf tSU-STO tBUF Cb VnL VnH (1) (2) (3) SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for repeated START Data setup time Data hold time (2) (3) TEST CONDITIONS MAX 400 (1) UNIT kHz s s s s s 0.9 300 300 s ns ns s s Rise time of both SDA and SCL signals Fall time of both SDA and SCL Setup time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) 1000 20 + 0.1 Cb (4) 0.6 1.3 400 pF V V (4) In master mode, the maximum speed is 375 kHz. Note that SDA does not have the standard I2C specification 300-ns internal hold time. SDA must be valid by the rising and falling edges of SCL. TI recommends that a 2-k pullup resistor be used to avoid potential timing issues. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU-DAT 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr-max + tSU-DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. Cb = total capacitance of one bus line in pF. SDA tf tLOW tr SCL tf tSU-DAT tHD-STA tSP tBUF tr tHD-DAT tHD-STA S tHIGH Sr tSU-STA tSU-STO P S T0114-01 Figure 8-4. Start and Stop Conditions Timing Waveforms Electrical Specifications 47 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 8.5.5.1 Recommended I2C Pullup Resistors It is recommended that the I2C pullup resistors RP be 4.7 k (see Figure 8-5). If a series resistor is in the circuit (see Figure 8-6), then the series resistor RS should be less than or equal to 300 . DVDD TAS3108/TAS3108IA RP SDA SCL VI(SDA) VI(SCL) IP RP IP External Microcontroller B0099-03 Figure 8-5. I2C Pullup Circuit (With No Series Resistor) DVDD TAS3108/TAS3108IA RP SDA or SCL VI RS (2) External Microcontroller IP RS (2) VS (1) B0100-03 (1) (2) VS = DVDD x RS/(R)S = RP). When driven low, VS << VIL requirements. RS 300 Figure 8-6. I2C Pullup Circuit (With Series Resistor) 8.5.6 Reset Timing (TAS3108/TAS3108IA) PARAMETER TEST CONDITIONS PLL0 = PLL1 = MICROCLK_DIV = 0 MIN 10 10 MAX UNIT ns ms control signal parameters over recommended operating conditions (unless otherwise noted) tw(RESET) tr(run) Pulse duration, RESET active Time to enable I2C RESET Start of Boot Sequence tw(RESET) Outputs Inactive tr(run) Enable I2C Start System T0029-02 NOTE: MCLK input = 12.288 MHz Figure 8-7. Reset Timing 48 Electrical Specifications www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 9 9.1 Application Information Schematics Figure 9-1 shows a typical TAS3108/TAS3108IA application. In this application the following conditions apply: * * * TAS3108/TAS3108IA is in clock-slave mode. The audio (SDIN1, SDIN2, SDIN3, SDIN4) and clock source (MCLKI) are external. MCLKI = 12.288 MHz Because MCLKI is sourced externally, the TAS3108/TAS3108IA crystal interface is not used. MCLKI and XTLI are logically ORed together, meaning that when the MCLKI pin is used, the XTALI pin must be grounded. I2C register 0x00 contains the default settings which means: - Audio data word size is 24-bit input and 24-bit output. - Serial data format is 2-channel, I2S for input and output. - I2C data transfer is approximately 400 kbps for both master and slave I2C interfaces. - PLL0 = PLL1 = PLL2 = 0 means that fDSPCLK is 11 x MCLKI = 135.2 MHz and that fI2CSCL = 375 kHz. - Sample frequency (fS) is 48 kHz, which requires that fLRCLK = 48 kHz and fSCLKIN = 3.072 MHz. Application code and data are loaded from an external EEPROM using the master I2C interface. Application commands come from the system microprocessor to the TAS3108/TAS3108IA using the slave I2C interface. * * * Good design practice requires isolation between the digital and analog power as shown. Power supply capacitors of 10 F and 0.1 F should be placed near the power supply pins AVDD (AVSS) and DVDD (DVSS). The TAS3108/TAS3108IA reset needs external glitch protection. Also, reset going HIGH should be delayed until TAS3108/TAS3108IA internal power is good (~200 s). This is provided by the 1-k resistor, 1-F capacitor, and diode placed near the RESET pin. It is recommended that a 4.7-F capacitor (fast ceramic type) be placed near pin 28 (VR_DIG). This pin must not be used to source external components. Application Information 49 TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 www.ti.com 1 0.01 F 2 3 4 47 5 6 7 8 Audio and Clock Source 9 10 47 47 47 47 10 10 System Microprocessor System Reset 10 k 10 k 11 12 13 14 15 16 17 18 19 AVSS VR_PLL XTALI XTALO MCLKI MICROCLK_DIV CS0 GPIO DVDD DVSS SDIN1 SDIN2 SDIN3 SDIN4 SDA1 SCL1 SDA2 SCL2 LRCLK TAS3108 (TAS3108IA) AVDD RESERVED PLL2 PLL1 PLL0 RESERVED RESET PDN DVDD DVSS VR_DIG SDOUT1 SDOUT2 SDOUT3 SDOUT4 SCLKOUT2 SCLKOUT1 MCLKO SCLKIN 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 3.3V_AVDD 1 k + System Reset 0.1 F 3.3 V 3.3 V 4.7 F 47 47 47 47 47 Audio Output 3.3 V 47 47 to DVDD EEPROM (Program Code and Data) TAS3108/ TAS3108IA Power Supply 3.3 V 10 F(1) + 0.1 F 3.3 3.3V_AVDD to AVDD 10 F(1) + 0.1 F Ferrite Bead S0123-01 (1) Capacitors should be placed as close as possible to the power supply pins. Figure 9-1. Typical Application Diagram 50 Application Information www.ti.com TAS3108/TAS3108IA AUDIO DSP SLES152A - OCTOBER 2005 - REVISED MARCH 2006 9.2 Recommended Oscillator Circuit TAS3108/TAS3108IA C1 Osc Circuit rd XO C2 XI AVSS S0114-01 * * * * * MCLKI and XTLI are logically ORed together, meaning that when the XTALI pin is used, the MCLKI pin must be grounded. Crystal type = parallel-mode, fundamental-mode crystal rd = drive-level control resistor - vendor specified CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal) CL = (c)1x C2)/(c)1 + C2) + CS (where CS = board stray capacitance, ~2 pF) 9.3 Recommended PCB Design for TAS3108IA Applications Automotive applications require that the TAS3108IA operates properly while in an ambient temperature range of -40 C to 105C. Under the high-temperature condition of 105C ambient, the TAS3108IA thermal pad must be soldered to a copper area on the PCB designed for thermal relief. High-temperature applications also require that the application be built on a high-K dielectric PCB. High-K dielectric PCB requirements for using TAS3108IA with soldered thermal pad: * 0.062 inch thick * Minimum 3-inch x 3-inch PCB * 2-oz. copper traces located on top of the board (0,071 mm thick) * Copper area located on the top and bottom of the PCB for soldering * Power and ground planes, 1-oz. copper (0,036 mm thick) * Thermal vias, 0,3-mm diameter, 1,5-mm pitch * Thermal isolation of power plane If the target application limits the ambient temperature to 0C to 70C (standard commercial temperature range), then the thermal pad does not need to be soldered to the PCB. For more information, see Texas Instruments documents PowerPADTM Thermally Enhanced Package (SLMA002) and PowerPADTM Made Easy (SLMA004). Application Information 51 |
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